1. Field of the Invention
The present invention relates to a display device for displaying an image by inputting a digital video signal. In particular, the present invention relates to a display device having light emitting elements. Further, the present invention relates to an electronic appliance that uses the display device.
2. Description of the Related Art
A display device having a light emitting element disposed in each pixel which performs display of an image by controlling light emitted from the light emitting elements is explained below.
The explanation throughout this specification uses elements (OLED elements) having a structure in which an organic compound layer for emitting light when an electric field is generated is sandwiched between an anode and a cathode, for the light emitting elements, but the present invention is not limited to this structure.
Further, the explanation within this specification uses elements that utilize light emitted when making a transition from singlet excitons to a base state (fluorescence), and those that utilize light emitted when making a transition from triplet excitons to a base state (phosphorescence).
Layers such as hole injecting layers, hole transporting layers, light emitting layers, electron transporting layers, electron injecting layers can be given as organic compound layers. Light emitting elements basically are shown by structures in which an anode, a light emitting layer, and a cathode overlap in this order. In addition, structures such as a structure in which an anode, a hole injecting layer, a light emitting layer, an electron injecting layer, and a cathode are overlapped in this order, and one in which an anode, a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, an electron injecting layer, and a cathode are overlapped in this order may also be used.
A display device is constituted by a display and peripheral circuits for inputting signals to the display.
The structure of the display is shown in a block diagram of FIG. 6.
In FIG. 6, the display 100 is constituted by a source signal line driver circuit 1107, a gate signal line driver circuit 1108, and a pixel portion 1109. The pixel portion has pixels disposed in a matrix shape.
Thin film transistors (hereafter referred to as TFTs) are arranged in each pixel. A method of placing two TFTs in each pixel and controlling light emitted from the light emitting element of each pixel is explained.
FIG. 7 shows a structure of a pixel portion of a display device.
Source signal lines S1 to Sx, gate signal lines G1 to Gy, and electric power source supply lines V1 to Vx are arranged in a pixel portion 700, and x columns and y rows (where x and y are natural numbers) of pixels are also placed in the pixel portion. Each pixel 700 has a switching TFT 701, a driver TFT 702, a storage capacitor 703, and a light emitting element 704.
The pixel is constituted by one source signal line S of the source signal lines S1 to Sx, one gate signal line G of the gate signal lines G1 to Gy, one electric power source supply line V of the electric power source supply lines V1 to Vx, the switching TFT 701, the driver TFT 702, the storage capacitor 703, and the light emitting element 704.
A gate electrode of the switching TFT 701 is connected to the gate signal line G, and either a source region or a drain region of the switching TFT 701 is connected to the source signal line S, while the other is connected to a gate electrode of the driver TFT 702 and to one electrode of the storage capacitor 703. Either a source region or a drain region of the driver TFT 702 is connected to the electric power source supply line V, while the other is connected to an anode or a cathode of the light emitting element 704. The electric power source supply line V is connected to one of the two electrodes of the storage capacitor 703, namely the electrode on a side to which the driver TFT 702 and the switching TFT 701 are not connected.
The anode of the light emitting element 704 is referred to as a pixel electrode, and the cathode of the light emitting element 704 is referred to as an opposing electrode, within this specification for cases in which the source region or the drain region of the driver TFT 702 is connected to the anode of the light emitting element 704. On the other hand, if the source region or the drain region of the driver TFT 702 is connected to the cathode of the light emitting element 704, then the cathode of the light emitting element 704 is referred to as the pixel electrode, and the anode of the light emitting element 704 is referred to as the opposing electrode.
Further, an electric potential imparted to the electric power source supply line V is referred to as an electric power source electric potential, and an electric potential imparted to the opposing electrode is referred to as an opposing electric potential.
The switching TFT 701 and the driver TFT 702 may be either p-channel TFTs or n-channel TFTs. However, it is preferable that the driver TFT 702 is a p-channel TFT, and that the switching TFT 701 is an n-channel TFT for cases in which the pixel electrode of the light emitting element 704 is the anode. Conversely, it is preferable that the driver TFT 702 is an n-channel TFT, and that the switching TFT 701 is a p-channel TFT if the pixel electrode is the cathode.
Operations during display of an image with the aforementioned pixel structure are explained below.
A signal is input to the gate signal line G, and the electric potential of the gate electrode of the switching TFT 701 changes, then a gate voltage is changed. The signal is input to the gate electrode of the driver TFT 702 by the source signal line S, via the source and drain of the switching TFT 701 which thus has been placed in a conductive state. Further, the signal is stored in the storage capacitor 703. The gate voltage of the driver TFT 702 changes in accordance with the signal input to the gate electrode of the driver TFT 702, then the source and drain are placed in a conductive state. The electric potential of the electric power source supply line V is imparted to the pixel electrode of the light emitting element 704 through the driver TFT 702. The light emitting element 704 thus emits light.
A method of expressing gradations with pixels having such a structure is explained. Gradation expression methods can be roughly divided into an analog method and a digital method. The digital method has advantages of being good at variation of TFTs. A digital gradation expression method is focused upon here. A time gradation method can be given as the digital gradation expression method. A time gradation driving method is explained in detail below.
The time gradation driving method is a method of expressing gradations by controlling the period that each pixel of a display device emits light. If a period for displaying one image is taken as one frame period, then one frame period is divided into a plurality of subframe periods.
Turn on and turn off, namely whether or not the light emitting element of each pixel is made to emit light or to not emit light, is performed for each subframe period. The period during which the light emitting element emits light in one frame period is controlled, and a gradation for each pixel is expressed.
The time gradation driving method is explained in detail using timing charts of FIG. 5. Note that an example of expressing gradations using a 4-bit digital image signal is shown in FIG. 5. Note also that FIG. 7 may be referred to regarding the structure of the pixel portion and the structure of the pixels, respectively. In accordance with an external electric power source (not shown in the figures), the opposing electric potential can be switched over between an electric potential on the same order as the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential), and an electric potential difference of the electric power source supply lines V1 to Vx on an order sufficient to make the light emitting element 704 emit light.
One frame period F is divided into a plurality of subframe periods SF1 to SF4. The gate signal line. G1 is selected first in the first subframe period SF1, and a digital image signal is input from the source signal lines S1 to Sx to each of the pixels having the switching TFTs 701 with gate electrodes connected to the gate signal line G1. The driver TFT 702 of each pixel is placed in an ON state or an OFF state by the input digital image signal.
The term “ON state” for a TFT in this specification indicates that the TFT is in a state in which there is a state of conduction between the source and the drain in accordance with a gate voltage. Further, the term “OFF state” for a TFT indicates that there is a non-conductive state between the source and the drain in accordance with the gate voltage.
The opposing electric potential of the light emitting elements 704 is set nearly equal to the electric potential of the electric power source supply lines V1 to Vx (electric power source electric potential) at this point, and therefore the light emitting elements 704 do not emit light even in pixels having their driver TFT 702 in an ON state. The aforementioned operations are repeated for all of the gate signal lines G1 to Gy, and a write-in period Ta1 is completed. Note that a period for write-in during the first subframe period SF1 is called Ta1. In general, a write-in period of a j-th sub-frame period SFj (where j is a natural number) is called Taj.
The opposing electric potential changes when the write-in period Ta1 is complete, so as to have an electric potential difference from the electric power source electric potential on an order so that the light emitting element 704 will emit light. A display period Ts1 thus begins. Note that the display period of the first subframe period SF1 is called Ts1. In general, a display period of the j-th sub-frame period SFj (where j is a natural number) is denoted by using a reference symbol Tsj. The light emitting elements 704 of each pixel are placed in a light emitting state or a non-light emitting state, corresponding to the input signal, in the display period Ts1.
The above operations are repeated for all of the subframe periods SF1 to SF4, one frame period F1 is completed. The length of the display periods Ts1 to Ts4 of the subframe periods SF1 to SF4 are set appropriately here, and gradations are expressed by an accumulation of the display periods of the subframe period during which the light emitting elements 804 emit light. In other words, the total amount of the turn on time within one frame period is used to express the gradations.
A method of generally expressing 2n gradations by inputting an n-bit digital video signal, is explained. One frame period is divided into n sub-frame periods SF1 to SFn at this point, for example, and the ratios of the lengths of the display periods Ts1 to Tsn of the sub-frame periods SF1 to SFn are set so as to be Ts1::Ts2:: . . . ::Tsn−1::Tsn=20::2−1:: . . . ::2−n+2::2−n+1. Note that the lengths of the write-in periods Ta1 to Tan are all the same.
Within one frame period, the gradation of the pixels in the frame period is determined by finding the total of the display period Ts during which a light emitting state is selected in the light emitting elements 704. For example, if the brightness for a case in which a pixel emits light during all of the display periods is taken to be 100% when n=8, then a brightness of 1% can be expressed if the pixel emits light in the display period Ts8 and in the display period Ts7. A 60% brightness can be expressed for cases in which the pixel emits light in the display periods Ts6, Ts4, and Ts1.
It is preferable that the display device has as little electric power consumption as possible here. Low electric power consumption is especially desirable if the display device is incorporated into a portable information device or the like to be utilized.
In this case, with respect to a display device, into which the 4-bit signal mentioned above is input to thereby display 24 gradations, gradations are expressed by using only the tipper order 1-bit signal (digital signal), a method of reducing the electric power consumption of the display device is used.
A timing chart showing a driving method of the display device in a display mode of this case is shown in FIG. 9. Signals are input to respective pixels in the first sub-frame period SF1. When the signals are input to all of the pixels, the opposing electric potential changes to have an electric potential difference from the electric power source electric potential so that the light emitting elements emit light. The light emitting elements of all of the pixels are thus placed in a light emitting state or a non-light emitting state. Operations in the first sub-frame period are the same as the operations performed in the above mentioned display mode.
Next, the digital image signal is also similarly written to all of the pixels in the write-in period of the second sub-frame period. However, in the following display period, the electric potential of the opposing electrode does not change so as to have an electric potential difference from the electric power source electric potential so that the light emitting element emit light. That is, the light emitting elements of the pixels do not emit light in the display period of the second sub-frame period, regardless of the signals input to the pixels. This period is denoted as non-display.
Operations in the second sub-frame period are similarly repeated in the third sub-frame period and in the fourth sub-frame period to thus complete one frame period. The period in which the pixels perform display during one frame period is only the first sub-frame period. The number of times that the light emitting elements of the pixels emit light can thus be lowered, and the electric power consumption of the display device can be reduced.
However, in such a display device, each pixel of the display device does not perform display in a period except a sub-frame period which is corresponding to an upper bit for expressing gradations without using information of lower bits, in each driver circuit (source signal line driver circuit and gate signal line driver circuit), write-in operation of the digital video signal to each pixel is performed. At this time, start pulses, clock pulses and the like are input to each driver circuit of the display device to thereby continue the operation.
Therefore, even gradation display is performed with a small amount of information, each-of the driver circuits repeatedly performs sampling of the digital image signal, which is the same as sampling operations in the first display mode. Electric power is therefore consumed for sampling, and there is a problem that the electric power consumption cannot be made smaller.
Furthermore, in the sub-frame periods except the sub-frame period during which display is actually performed, the pixels are all uniformly in a non-display state during which light is not emitted. There is therefore a problem that the proportion of the effective display period in one frame period is small.